1. Field of the Invention
The present invention relates to a memory device. In particular, the present invention provides a method for manufacturing a semiconductor device, and more specifically to a method for manufacturing a semiconductor device wherein a first alignment key is formed using a step difference occurring during a process of forming a device isolation film on a scribe lane, and a second alignment key is formed on the scribe lane using the first alignment key during a process of forming a recess gate region on a cell region as to skip a key open process, thereby reducing a total around time of manufacturing a semiconductor device and a manufacturing cost for the semiconductor device.
2. Discussion of the Related Art
FIGS. 1a through 1e are cross-sectional views illustrating a conventional method for manufacturing a semiconductor device.
Referring to FIG. 1a, a trench (not shown) defining a device isolation region is formed on a semiconductor substrate 10 having a cell region and a scribe lane. Next, an oxide film (not shown) filling up the trench is formed, and then the oxide film is polished until the semiconductor substrate 10 is exposed to form a device isolation film 20 in the cell region 1000a and the scribe lane 1000b. At this time, since a pattern density in the scribe lane is low as compared to that of the cell region, a step difference on the device isolation film 20 in the scribe lane 1000b occurs and serves as an alignment key 25. The step difference of the alignment key 25 from the surface of the semiconductor substrate 10 ranges 250 Å to 350 Å.
Referring to FIGS. 1b and 1c, a photoresist film pattern 30 only exposing the scribe lane 1000b is formed on the semiconductor substrate 10. Next, a key open process is performed on the device isolation film 20 in the scribe lane 1000b using the photoresist film pattern 30. That is, the alignment key 25 is etched using the photoresist film 30 in the cell region 1000a as an etching mask by a predetermined thickness to make the step difference of the alignment key 25 deeper. Thereafter, the photoresist film pattern 30 is removed. The key open process includes a key open photo process, a key open etching process, a photoresist removing process and a subsequent cleaning process.
Referring to FIG. 1d, a hard mask layer 40 is formed on the entire surface of the semiconductor substrate 10 having the cell region 1001a and the scribe lane 1000b. The hard mask layer 40 is a polysilicon layer.
Referring to FIG. 1e, the hard mask layer 40 is etched using a recess gate mask (not shown) to form a hard mask layer pattern (not shown) defining a recess gate region 50 in the cell region 1000a. Next, the exposed semiconductor substrate 10 is etched using the hard mask layer pattern as an etching mask by a predetermined thickness to form the recess gate region 50 in the cell region 1000a, and then the hard mask layer pattern is removed.
According to the above conventional method for manufacturing a semiconductor device, a further step difference is formed using a key open process on the alignment key formed in the process forming the device isolation film, and then used in a subsequent process forming a gate. However, the key open process has four additional processes such as a key open photo process, a key open etching process, a photoresist removing process and a subsequent cleaning process. Accordingly, there is a problem of increasing TAT (time around time) for manufacturing a semiconductor device and manufacturing cost of the semiconductor device.